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Integrated Circuit Systems, Inc.
ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Four 3.3V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.57ps (typical) * RMS phase noise at 156.25MHz (typical) Phase noise: Offset Noise Power 100Hz ............... -95.5 dBc/Hz 1KHz ................ -118 dBc/Hz 10KHz ................ -126 dBc/Hz 100KHz .............. -126.6 dBc/Hz * Full 3.3V supply mode * -30C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS843004-01 is a 4 output LVPECL synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, 62.5MHz. The ICS843004-01 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843004-01 is packaged in a small 24-pin TSSOP package.
ICS
FREQUENCY SELECT FUNCTION TABLE
Inputs M Divider N Divider Value Value 25 4 25 25 25 5 10 not used M/N Divider Value 6.25 5 2.5 Output Frequency (25MHz Ref.) 156.25 125 62.5 not used
PIN ASSIGNMENT
nQ1 Q1 VCCo Q0 nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC F_SEL1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 VEE VCC nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT
F_SEL1 F_SEL0 0 0 1 1 0 1 0 1
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL
Pulldown
ICS843004-01
2
F_SEL[1:0]
TEST_CLK Pulldown
25MHz
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Q0 Top View
nQO Q1 nQ1
1
1
0 0 /4 0 1 /5 1 0 /10 1 1 not used
XTAL_IN
OSC
XTAL_OUT nXTAL_SEL Pulldown
0
Phase Detector
VCO 625MHz (w/25MHz Reference)
0
Q2 nQ2
M = 25 (fixed)
Q3 nQ3 MR Pulldown
843004AG-01
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REV. B MAY 6, 2005
Integrated Circuit Systems, Inc.
ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Type Description Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Negative supply pins. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 22 4, 5 6 Name nQ1, Q1 VCCO Q0, nQ0 MR Power Ouput Input Output
7 8 9 10, 12 11, 18 13, 14 15, 19 16 17 20, 21 23, 24
nPLL_SEL nc VCCA F_SEL0, F_SEL1 VCC XTAL_OUT, XTAL_IN VEE TEST_CLK nXTAL_SEL nQ3, Q3 Q2, nQ2
Input Unused Power Input Power Input Power Input Input Output Output
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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REV. B MAY 6, 2005
Integrated Circuit Systems, Inc.
ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 70C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -30C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Included in IEE Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 135 15 Units V V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -30C TO 85C
Symbol VIH VIL Parameter Input High Voltage nPLL_SEL, nXTAL_SEL, Input F_SEL0, F_SEL1, MR Low Voltage TEST_CLK TEST_CLK, MR, Input nPLL_SEL, nXTAL_SEL, High Current F_SEL0, F_SEL1 TEST_CLK, MR, Input nPLL_SEL, nXTAL_SEL, Low Current F_SEL0, F_SEL1 Test Conditions Minimum Typical 2 -0.3 -0.3 VCC = VIN = 3.465V Maximum VCC + 0.3 0.8 1.3 150 Units V V V A
IIH
IIL
VCC = 3.465V, VIN = 0V
-5
A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -30C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
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REV. B MAY 6, 2005
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ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical Maximum 25 50 7 Units MHz pF
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. Fundamental
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -30C TO 85C
Symbol fOUT Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz (1.875MHz - 20MHz) 0.57 0.63 0.81 300 600 51 RMS Phase Jitter; NOTE 3 Output Rise/Fall Time 125MHz (1.875MHz - 20MHz) 62.5MHz (1.875MHz - 20MHz) tR / tF 20% to 80% Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] =10 Minimum 140 112 56 Typical Maximum 170 136 68 30 Units MHz MHz MHz ps ps ps ps ps %
tsk(o) tjit(O)
odc Output Duty Cycle 49 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Phase jitter is dependent on the input source used.
843004AG-01
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REV. B MAY 6, 2005
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ICS843004-01
FEMTOCLOCKSTMCRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 62.5MHZ
0 -10 -20 -30 -40 -50
10Gb Ethernet Filter 62.5MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.81ps
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -180 -190 100 1k 10k -170
Raw Phase Noise Data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ
-10 -20 -30 -40 -50
0
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
OFFSET FREQUENCY (HZ)
843004AG-01
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Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
10Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.63ps (typical)
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
REV. B MAY 6, 2005
Integrated Circuit Systems, Inc.
ICS843004-01
FEMTOCLOCKSTMCRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
-10 -20 -30 -40 -50
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.57ps
0
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
1M 10M 100M
OFFSET FREQUENCY (HZ)
843004AG-01
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REV. B MAY 6, 2005
Integrated Circuit Systems, Inc.
ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VCC , VCCA, VCCO
Qx
SCOPE
nQx Qx nQy
LVPECL
nQx
VEE
Qy
tsk(o)
-1.3V0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
Noise Power
Phase Noise Mask
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0:nQ3 Q0:Q3
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843004AG-01
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REV. B MAY 6, 2005
Integrated Circuit Systems, Inc.
ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843004-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
843004AG-01
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REV. B MAY 6, 2005
Integrated Circuit Systems, Inc.
ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
CRYSTAL INPUT INTERFACE
The ICS843004-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
ICS843004-01
Figure 3. CRYSTAL INPUt INTERFACE
LAYOUT GUIDELINE
Figure 4 shows a schematic example of the ICS843004-01. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used. The C1=27pF and C2=33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy.
3.3V VCC R2 10 VCCA Zo = 50 Ohm C3 10uF C4 0.01u VCC VCCO C6 0.1u 12 11 10 9 8 7 6 5 4 3 2 1 Zo = 50 Ohm C7 0.1u R4 82.5 +
R3 133
R5 133
Logic Control Input Examples
VDD
VDD
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
XTAL_OUT XTAL_IN VEE TEST_CLK nXTAL_SEL VCC VEE nQ3 Q3 VCCO Q2 nQ2
RU1 1K
RU2 Not Install
F_SEL1 VCC F_SEL0 VCCA NC nPLL_SEL MR nQ0 Q0 VCCO Q1 nQ1
Set Logic Input to '1'
Set Logic Input to '0'
R6 82.5
VCC=3.3V VCCO=3.3V
R7 133 Zo = 50 Ohm
3.3V
U1 ICS843004-01
R9 133
13 14 15 16 17 18 19 20 21 22 23 24
+ VCC
C1 27pF
C9 0.1u
VCCO
C2 33pF
X1 25MHz 18pF
Zo = 50 Ohm
-
R8 82.5 C8 0.1u
R10 82.5
FIGURE 4. ICS843004-01 SCHEMATIC EXAMPLE
843004AG-01
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ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843004-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.588W * 65C/W = 123.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 24-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
843004AG-01
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REV. B MAY 6, 2005
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ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX L CC_MAX L [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. B MAY 6, 2005
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ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS843004-01 is: 3183
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FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. B MAY 6, 2005
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ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS843004A01 ICS843004A01 Package 24 Lead TSSOP 24 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature -30C to 85C -30C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843004AG-01 ICS843004AG-01T
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843004AG-01
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ICS843004-01
FEMTOCLOCKSTM CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev B
Table T5
Page 4
Description of Change AC Characteristics Table - deleted Propagation Delay row.
Date 5/6/05
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